1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to the testing of memories embedded on an integrated circuit.
2. Description of the Related Art
Many integrated circuits (IC's) include one or more memory arrays implemented thereupon. For example, microprocessors incorporate a number of different memory arrays, including multiple cache memories (e.g., L1 and L2 cache memories, an instruction cache memory, a data cache memory, etc.), a translation lookaside buffer, register files and associated register maps (for mapping logical register names to physical register names), FIFO (first-in, first-out) memories, content addressable memories (CAM's) and so forth. In some modern microprocessors, the number of embedded memory arrays can exceed 100. Other types of IC's, such as application specific integrated circuits (ASIC's) can include a similar number of memory arrays. These memory arrays may differ with each other in type, capacity, and physical organization.
Each of the different memory arrays is subject to certain types of faults/defects. These types of faults include coupling faults, pattern sensitive faults, stuck open faults, and so forth. Thus, testing of these memory arrays is required in order to ensure that they are free of defects. This testing is typically accomplished by BIST (built-in self-test) controllers embedded on the same IC as the memory arrays.
Certain types of memory array defects (e.g., pattern sensitive faults, coupling defects) may be related to the physical organization of a memory array. Accordingly, for a BIST to be effective, it must take into account the physical organization of the memory when generating sequences of address for reads and writes. If the physical organization is not taken into account, the BIST may fail to fully exercise those fault modes that are dependent thereon.
In implementing BIST controllers to test memory arrays, multiple approaches may be taken. However, each of these approaches has drawbacks. If memory BIST controllers are to take into account the physical organization of the various embedded memory arrays, a significant amount of logic may be required. This can result in a separate memory BIST controller for each of the different memory arrays or different types (by physical organization) of memory arrays. Alternatively, a single memory BIST controller with logic to account for each of the different types of arrays (according to physical organization) may be implemented. However, both of these solutions may require a prohibitive amount of die area on an IC, and thus may be impractical for IC's with a large number of embedded memory arrays having different physical organizations.
Alternatively, a smaller, single memory BIST controller that addresses each memory array using logical addresses may be implemented. However, this solution may be unsatisfactory from a test point of view, as it does not take into account the physical organization of the memory and may thus fail to exercise those failure modes which are dependent thereon.
Accordingly, with the increasing amount of functionality implemented on a single IC and corresponding requirements for additional memory arrays, the BIST solutions discussed above may be unsatisfactory, if not unfeasible altogether.